This invention relates to a semiconductor apparatus and a manufacturing method therefor, and more particularly to a semiconductor apparatus which incorporates a gate electrode having its side and bottom surfaces covered with gate insulator films, and a manufacturing method therefor to which a high temperature treatment is applicable.
This application is based on Japanese Patent Application No. 8-356493, filed on Dec. 26, 1996, the contents of which is cited herein by reference.
In a MOS (metal oxide semiconductor) transistor using a SiO.sub.2 film as a gate oxide film, it is important to thin the gate oxide film more than ever, in order to enhance the performance of the short channel transistor. It is considered, however, a problem in practical use to thin the gate oxide film by more than a thickness (e.g. about 3 nm or less) at which direct tunneling will occur.
As a method for solving the problem, it is proposed to form the gate oxide film of a so-called "high dielectric film" (such as a Ta.sub.2 O.sub.5 film) in place of the SiO.sub.2 film, in order to reduce the SiO.sub.2 equivalent film thickness and at the same time to restrain a leak current (due to direct tunneling) between the gate electrode and the substrate or a source and drain region of the transistor.
If in the transistor using the high dielectric film, however, a high temperature step ranging from 800-1000.degree. C. (including an annealing step to activate a source/drain ion implantation layer, a step for reflowing an interlayer film, etc.) is performed after the high dielectric film as the gate oxide film and a gate electrode made of a metal are formed, interface reaction will occur between Si substrate and the high dielectric film or between the high dielectric film and the gate electrode. Therefore, it is difficult for the transistor with the high dielectric film to endure the high temperature step, and the high dielectric film may well degrade. Accordingly, a transistor of high electric characteristics is hard to obtain.
Referring to FIGS. 1A and 1B, the above-described conventional problems will be explained in more detail. In these figures, reference numeral 31 denotes a silicon substrate, reference numeral 32 an element isolating region formed by the STI (Shallow Trench Isolation), reference numeral 33 a gate insulating film, reference numeral 34 a gate electrode, and reference numeral 35 a source/drain layer.
If, for example, the source/drain layer 35 is formed before the gate electrode 34, to protect the gate electrode 34 from a heat treatment performed for obtaining the layer 35, it is possible that the source/drain layer 35 will not be aligned with the gate electrode 34 as shown in FIG. 1A. This is a serious problem. Further, it must be considered how to execute, during a flattening step, a heat treatment such as a reflowing treatment to be performed after the gate electrode 34 is formed.
On the other hand, when the gate electrode 34 is formed before the source/drain layer 35 as in the prior art, it is necessary to form a gate insulator film 33 by interposing a high dielectric film between SiO.sub.2 films as shown in FIG. 1B, in order to enable the gate electrode to endure a high temperature step such as a step for activating the source/drain layer 35 or for reflowing the interlayer film. Thus, the total thickness of the gate insulator film inevitably increases.
In addition, to increase the breakdown voltage between the gate electrode 34 and the source/drain layer 35 and to enhance the reliability of the element, post-oxidation is generally performed after the gate electrode 34 is formed. The composition of the high dielectric film changes after the post-oxidation step (performed at, for example, about 900.degree. C. for about 30 minutes), with the result that the leak current of the gate insulator film 33 may well increase, which means degradation in the characteristics of the gate insulator film.
As described above, where a high dielectric film is used as the gate insulator film, it may well degrade since it does not have a heat resistance sufficient for a high temperature treatment required to form the semiconductor apparatus. Accordingly, a transistor of excellent electric characteristics is hard to obtain.